1. Field of the Invention
The present invention relates generally to computer communication protocols, and more specifically to a message passing protocol which is integrated with a cache coherence protocol in a multiprocessing computer system.
2. Discussion of Background Art
Multiprocessor data computer systems consist of a plurality of processor nodes communicating over a high-speed interconnection network. Each processor node typically includes a processor and local Random Access Memory (RAM). A computational problem is divided among processor nodes so that the utilization of particular resources available at different processor nodes is maximized. Dividing the problem among processor nodes also reduces the time needed to produce a result and thereby expedites the computation. However, this division of labor necessarily implies that a process running on one processor node may depend on the results of computations being performed at another processor node. The various processes then must communicate over the interconnection network to exchange information relevant to their particular problems, and must also synchronize the processes.
The performance level of a multiprocessor system depends on the speed with which processors can communicate with one another. In the sharedmemory paradigm, communication is very fast because each processor can simply read what the other processors have written. However, this model does not offer communicating processes any protection from interfering with one another by inadvertently overwriting each other's critical memory areas. In the message-passing model, on the other hand, each processor can only access its own memory and can only communicate with other processors by explicitly building up a message and sending it to the other processor. This model offers the communicating processors protection from one another, because they cannot write to each other's memory. However, this model is also inefficient because typically the operating system must be invoked on both sides of the transfer (sender and receiver). These operating system calls slow communication between the processors. It is thus desirable to allow communicating processes access to designated areas in each other's memory directly but at the same time protecting against inadvertent accesses to other areas of memory, all without the need for operating system intervention on the receiving side.
A mechanism that allows one processor to protect itself from having another processor corrupt its memory inadvertently due to a hardware or software fault is disclosed in U.S. Pat. No. 5,448,698, issued Sep. 5, 1995 to Wilkes. The Wilkes protection-check mechanism uses a protection table at the target that specifies a key for a number of memory areas. The mechanism disclosed in the Wilkes patent has the disadvantage that a table must be built into the hardware and requires storage space that inherently contains only a limited number of entries.